Not applicable.
Not applicable.
1. Field of the Invention
The present invention generally relates to a computer system that contains multiple processors and a main power supply. More particularly, the invention relates to an apparatus and method to sequentially power-on the processors of the computer system and thereby reduce the current source requirements of the power supply and power supply surges.
2. Background of the Invention
Modern day computer systems use multiple power voltages to power the processor in the computer system. In a computer system requiring 2.7 volts, 3.3 volts, 5 volts, 12 volts or any other appropriate voltage, during power-on the computer system""s power management circuits apply power to the processor in the proper sequence required by the processor. Similarly, in current multiprocessor systems (i.e., computer systems with more than one processor) power management circuits turn on the 2.7 volt, 3.3 volt, 5 volt, 12 volt, and any other appropriate voltage supplies in the proper sequence required for each processor. In multiprocessing computer systems, all processors of the computer system are powered on together.
Higher processor clock speeds typically require more power. Thus, as processor clock speeds increase, so does the power requirement. Moreover, currently available multiprocessing computer systems are expanding into 8, 16, 32 processors and beyond. The number of processors and processor power demands are increasing such that current surges during power-on are becoming an important issue.
FIG. 1 shows a plot of power supply current versus time for power-on of a multiprocessing computer system containing four processors in which all processors are powered on simultaneously. As can be seen from FIG. 1, multiprocessing computer system designs can have a significant current surge Peak_A during power-on at time T that requires a power source much greater than the standard Norm amperage shown in FIG. 1. In one preferred embodiment, the Norm amperage may be in the range between 13 to 17 amperes and preferably 15 amperes.
It would be advantageous if a simple method and apparatus could be used to sequentially power-on the processors of a multiprocessing computer system to reduce the peak instantaneous current surge occurring at power-on. It would also be advantageous for such an apparatus to automatically (i.e., without user interaction) power-on the processors in a not noticeable time period to reduce the peak instantaneous current surge and thus minimize the requirements of the power supply. Despite the apparent advantages of such a system, to date no such system has been implemented.
The problems noted above are solved in large part by a system and method that sequentially powers on the processors of a multiprocessing computer system to reduce the current sourcing requirements of the power supply and eliminate power supply surges. According to the exemplary embodiment of the invention, the computer system includes a power supply coupled to a control logic, the power supply including a power_good output signal and Power output lines. The power_good signal notifies the control logic when the power supply Power output lines have stabilized. The computer system also includes a number of voltage regulator modules (xe2x80x9cVRMxe2x80x9d) coupled to the control logic, with each VRM receiving a power good signal from the control logic. Each VRM transmits voltage to a processor to power-on the processor. Each VRM also transmits to its processor and to the control logic a voltage regulator module power good (xe2x80x9cVRMP_Gxe2x80x9d) signal. The VRMP_G signal indicates that the VRM voltage output lines have stabilized. The control logic of the computer system may be a state machine implemented in a programmable array logic (xe2x80x9cPALxe2x80x9d) or other programmable logic device (xe2x80x9cPLDxe2x80x9d). The control logic controls the sequential power-on of the processors in the multiprocessing computer system.
In accordance with the exemplary embodiment, sequential power-on of the processors in the multiprocessing computer system comprises the following steps. First, the power supply asserts its power_good signal to the control logic after the power supply output lines have stabilized. Next, the control logic places all processors of the computer system into a reset state. The control logic asserts a control logic power_good signal to a first VRM. Next, after waiting a first programmable delay for the VRM to stabilize its voltage output lines to appropriate levels, the VRM asserts a VRM power_good signal to the VRM""s processor and the control logic after the VRM voltage output lines have stabilized. The control logic after waiting a second programmable delay for the processor to reach a stable electrical state determines whether all processors are powered on. If all processors are not powered on, the control logic drives another control logic power_good signal to the next VRM and repeats the steps given above. After all processors have been powered on and after waiting a third programmable delay, the control logic takes all processors of the multiprocessing computer system out of reset to begin hardware initialization and Power-On-Self-Test (xe2x80x9cPOSTxe2x80x9d).